1. Field of the Invention
The present invention relates to memory units used in multiprocessor systems and methods for using memory units in multiprocessor systems. More particularly, the present invention is directed to a method and apparatus associated with a memory unit connected to a tightly coupled multiprocessor system that includes a split model bus and executes atomic transactions in a synchronous mode using semaphore variables or lock variables.
2. Description of the Related Art
Recently, multiprocessor systems have become more popular and employ plural processors connected in a way that allows the multiprocessor system to offer greater processing capability than systems employing a single processor. Such multiprocessor systems employ a few processors and distribute the processing demands on the respective processors by assigning plural functions to the processors and later combining the results. In order to capitalize on the benefits of this parallel processing approach, the processors must be able to communicate with one another effectively and share resources effectively. To this end, conventional multiprocessor systems employ two alternative system architectures named tightly coupled multiprocessor systems and loosely coupled multiprocessor systems.
FIG. 1 shows an example of a block diagram showing the loosely coupled multiprocessor system. Plural processors 2a, 2b . . . are directly connected to respective dedicated local memories 1a, 1b . . . The plural processors 2a, 2b . . . are interconnected by a system bus 3 in this loosely coupled multiprocessor system.
FIG. 2 shows an example of a block diagram showing the tightly coupled multiprocessor system. Plural processors 4a, 4b . . . and a shared memory 6 are connected by a system bus 5. Certain efficiencies, such as a lower number of memories, exist in the tightly coupled multiprocessor system that are not present in the loosely coupled multiprocessor system of FIG. 1. However, memory contention problems exist in the tightly coupled multiprocessor system that are not present in the loosely coupled multiprocessor system. The memory contention problems result from the plural processors 4a, 4b . . . accessing and changing a common block of memory in the shared memory 6. This so called access contention occurs because each of the plural processors 4a, 4b . . . has independent access to the shared memory 6. Therefore, arbitration is needed in the tightly coupled multiprocessor system so as to avoid the situation where one of the processors accesses a memory block at the same time as another processor, and then both processors attempt to change the contents of the same memory block.
In access arbitration, control operations or control signals between the processors 4a, 4b . . . synchronize the tightly coupled multiprocessor system. This arbitration employs semaphore variables (or lock variables) stored in the shared memory 6 to control which of the processors 4a, 4b, . . . have control over accessing and changing a predetermined portion of the shared memory 6. Conventional semaphore variables P(s), V(s) are functions of non-negative integer "s", where a semaphore operation is carried out in the basis of following expressions:
If P(s) is s&gt;=1 then s=s-1, and go to next operation, PA1 If v(s) is s=0 then s&gt;=1, and then wait.
When lock variables are used, the lock variables function as flags that define whether a processor has permission to access the memory 6 as determined by a test-and-set operation.
Further explaining the risk of memory contention, unless some convention is set between the respective processors for honoring a globally recognized state of the shared memory 6, a block of memory that is currently accessed by a first processor may be rewritten during a memory access operation by a second processor, thus rendering the original information extracted by the first processor useless, because it would be unclear as to what is the globally recognized state of the memory (i.e., that extracted, and perhaps changed by the first processor or the new contents inserted by the second processor). Therefore, the semaphore variables or lock variables are stored in the shared memory 6 as a convention for determining which of the processors are authorized to change the state of the memory.
Using the semaphore or lock variable, when a processor tries to rewrite a memory block, the processor recognizes whether lock variables or semaphore variables may be rewritten or not by accessing the semaphore variables or lock variables. When the bytes may not be rewritten, the processor rewrites the semaphore variables or lock variables and performs a rewrite operation. As a result, a synchronization of when the semaphore variables or lock variables are recognized and rewritten must be performed.
A series of processor steps between a recognition event and a rewrite event are inseparable and are called atomic transaction. Moreover, the atomic transaction ensures that a series of operations may be completed as a group, but if not, perhaps as a result of being interrupted mid-stream, the series of operations are discontinued and the state of the memory is returned to the original state before the atomic transaction was initiated. In this way the atomic transaction may be viewed as an "all or nothing" operation that preserves the state of the memory if all of the operations cannot be completed.
However, when one of the processors accesses and rewrites the semaphore variables or the lock variables while another processor is executing a series of recognition and rewrite operations for same variable, the operations become confused for lack of proper synchronization with respect to changing the semaphore or lock variables. Korth, H., F., et al., Database System Concepts, second edition, McGraw-Hill Inc., pp. 313-423, 1991, provides a general discussion on recovery and atomicity, the entire contents of this reference being incorporated herein by reference. Myers, B., et al., Mastering Windows NT Programming, Sybex Inc., 1993 provides a general discussion on semaphore variables, the entire contents of this reference being incorporated herein by reference.
One conventional solution to solving the problem of access synchronization, attempts to not separate the recognizing operation from the rewriting operation and prohibits the other processors from executing additional operations during the recognition and rewriting operations. Japanese patent application 64-210037 discloses such a non-separated operation between recognition and rewrite for lock variables in the atomic transaction. Moreover, when a processor operates the recognition and rewrite for the shared memory 6, a bus that interconnects the respective processors is locked and accesses from the other processors for the shared memory are prohibited. In Japanese patent application 64-210037 it is explained that until the atomic transaction is complete, the bus is locked so as to prohibit another processor from accessing the bus.
As shown FIG. 3, a conventional multiprocessor system uses a split model bus that includes low performance bus 13 and a a high performance bus 11 for interconnecting processors 9a, 9b . . . and other high speed devices such as the shared memory 10 and the hard disk apparatus 14 that includes a hard disk 7 and a hard disk controller 8, as shown. The low speed bus 13 connects to the system bus 11 by way of a bus adapter 12. The low speed bus 13 is used to allow plural input-output devices and peripherals to have access to the system. The split model bus system can separately and simultaneously communicate address data and another data on the respective buses.
However, as recognized by the present inventor, the atomic transaction as discussed in the above described Japanese patent application 64-210037 impairs the ability to separately and simultaneously communicate in the split model bus system until the atomic transaction is complete.